The present invention relates to a processing unit equipped with a function of controlling an access (load/store) to a system memory. Particularly, the invention relates to a processing unit capable of improving its processing capacity by reducing the number of synchronization control required at the time of changing over interruption levels (running level).
In recent years, along with rapid development of computer technologies, there has been progressed an accelerated increase in the capacity of software to be executed and the capacity of a memory to higher levels. Accordingly, in order to meet this trend of increase in capacities, processing units to be mounted on computers are also required to have higher performance capacities that can execute processing at higher speed.
FIG. 24 is a block diagram that shows a structure of a conventional processing unit. FIG. 24 shows a structure that one system memory 7 is shared by n processing units 11 to 1n. Each of the processing units 11 to 1n makes access to the system memory 7 (or a cache memory 61) according to load/store instructions, thereby to execute loading/storing of data. Further, each of the processing units 11 to 1n executes various kinds of processing based on processing instructions such as an addition instruction and a subtraction instruction.
In the processing unit 11, an instruction buffer 21 buffers the processing instructions and load/store instructions in the sequence of issuance of the instructions. An instruction issuing unit 31 issues the processing instruction or the load/store instruction buffered in the instruction buffer 21 to a processor 41 or to a memory access unit 51. The processor 41 executes various kinds of processing according to the processing instruction issued from the instruction issuing unit 31. The processor 41 also outputs a busy signal BUSY1 that shows that the processor 41 is currently executing a processing, to the instruction issuing unit 31. After the processor 41 has finished the processing, the processor 41 stops outputting the busy signal BUSY1.
The memory access unit 51 stores data into the system memory 7 (or the cache memory 61) or loads data from the system memory 7 (or the cache memory 61), according to the load/store instruction issued from the instruction issuing unit 31. The memory access unit 51 also outputs a busy signal BUSY1 that shows that the memory access unit 51 is currently executing a load/store of data, to the instruction issuing unit 31. After the memory access unit 51 has finished the load/processing, the memory access unit 51 stops outputting the busy signal BUSY1.
The processing unit 1n has a structure and functions that are the same as the structure and the functions of the processing unit 11. In other words, the processing unit 1n consists of an instruction buffer 2n, an instruction issuing unit 3n, a processor 4n, a memory access unit 5n, and a cache memory 6n.
An interruption level in the processing units 11 to 1n will be explained next with reference to FIG. 25A to FIG. 25C. When there has been a request for an interruption processing during a period while one of the processing units 11 to 1n is executing a processing (an arithmetic processing, or a load/store processing), the interruption level is a phase of the processing for executing this interruption processing by suspending the processing of the processing unit. As an example, FIG. 25A shows four stages of interruption levels from an interruption level 1 to an interruption level 4.
According to the example shown in FIG. 25A, the interruption level 1 is a level that shows a state that there is no request for an interruption. When an interruption has occurred during the execution of a processing at the interruption level 1, the interruption level 1 is changed to the interruption level 2 as shown in FIG. 25B. For example, when an interruption has occurred at time t1 during the execution of a processing at the interruption level 1, the interruption level 1 is changed to the interruption level 2. Thus, the processing at the interruption level 1 shifts to the interruption processing at the interruption level 2 so that the interruption processing at the interruption level 2 is executed at and after the time t1. When the interruption processing has been finished at the time t2, the interruption level returns to the interruption level 1 from the interruption level 2. In this way, the interruption processing at the interruption level 2 finishes, and the processing returns to the interruption level 1.
When there has occurred a further interruption during the execution of an interruption processing at the interruption level 2, the interruption level 2 shifts to the interruption level 3 as shown in FIG. 25A. Similarly, when a further interruption has occurred during the execution of an interruption processing at the interruption level 3, the interruption level 3 shifts to the interruption level 4. On the other hand, when the interruption processing at the interruption level 4 has been finished, the interruption level returns from the interruption level 4 to the interruption level 3. When the interruption processing at the interruption level 3 has been finished, the interruption level returns from the interruption level 3 to the interruption level 2. Similarly, when the interruption processing at the interruption level 2 has been finished, the interruption level returns from the interruption level 2 to the interruption level 1.
According to the conventional processing unit, in order to improve the processing capacity, there has been introduced a concept called a memory access sequencing model (hereinafter to be referred to as a memory model) that prescribes a relationship between the sequence of issuing load/store instructions and the sequence of actually executing the load/store instructions. For example, there exist two kinds of memory models (0, 1) as shown in FIG. 26.
In the memory model 0 shown in FIG. 26, the sequence of issuing load/store instructions is the same as the execution sequence of the issued load/store instructions. Thus, this is a most severe control model. Therefore, in the memory model 0, it is not possible to bypass the execution, that is, it is not possible to replace the issued sequence of the load/store instructions at the execution stage. More specifically, in the case of the memory model=0, when the load/store instructions have been issued in the sequence of the load/store instructions A0, B0, C0 and D0, these load/store instructions A0, B0, C0 and D0 are executed in the same sequence as the issued sequence, as shown in FIG. 27A.
On the other hand, the memory model 1 shown in FIG. 26 is a model that has no limit between the sequence of issuing load/store instructions and the sequence of executing the issued load/store instructions. Therefore, in the memory model 1, it is possible to bypass the execution, that is, it is possible to replace the issued sequence of the load/store instructions at the execution stage. More specifically, in the case of the memory model =1, when the load/store instructions have been issued in the sequence of the load/store instructions A1, B1, C1 and D1, it is possible to execute these load/store instructions by replacing the sequence of the load/store instruction B1 with the load/store instruction C1, as shown in FIG. 27B.
The replacement of the execution (bypass execution) is effective when the execution of the later-issued load/store instruction C1 earlier than the execution of the earlier-issued load/store instruction B1 can improve the processing speed. In other words, in the case of the memory model 1, the load/store instructions are executed sequentially in the order of the instructions that can be executed, regardless of the issued sequence. Therefore, it is possible to reduce the time of waiting for the execution of the instructions, which can improve the total processing speed.
On the other hand, in the memory model=0 (refer to FIG. 27A), it is not possible to replace (bypass) the order of executing the load/store instructions. More specifically, as shown in FIG. 27A, even if it is possible to improve the processing speed when the load/store instruction C0 issued later is executed prior to the execution of the earlier-issued load/store instruction B0, it is not possible to replace the order of executing the load/store instruction B0 with the order of executing the load/store instruction C0. Therefore, in the case of the memory model 0, there is a tendency that the time of waiting for the execution of the load/store instructions becomes long, which lowers the total processing speed.
Further, in the conventional processing unit, the above memory models are set according to the interruption levels shown in FIG. 25A. For example, in the case of the interruption level 1, the memory model 0 (refer to FIG. 26) is set. When the interruption level 1 has been changed to the interruption level 2, the memory model 0 shifts to the memory model 1. However, as described later, there is a case where the memory model does not shift even if the interruption level has been changed.
The operation of the conventional processing unit will be explained next with reference to a flowchart shown in FIG. 28. In this case, it is assumed that the processing unit 11 shown in FIG. 24 is executing the interruption processing at the interruption level 2 shown in FIG. 25B. In this operation state, at step SA1 in FIG. 28, the instruction issuing unit 31 makes a decision as to whether a synchronization instruction has been issued or not.
When an interruption level has been changed, this synchronization instruction is issued to restrict the issuing of the instructions buffered to the instruction buffer 21 after this change until when the execution of all the instructions buffered in the instruction buffer 21 before the change has been finished. In other words, this synchronization instruction is an instruction to complete the execution of all the instructions before the synchronization point, prior to the execution of the instructions after the synchronization point. In short, the synchronization instruction is an instruction to execute a synchronization control between the change in the interruption level and the issuing of the instructions. Accordingly, in the conventional processing unit, the synchronization instruction is issued without exception when the interruption level has been changed.
It is assumed that the interruption level has not been changed, and that the synchronization instruction has not been issued either. The instruction issuing unit 31 then makes a decision of xe2x80x9cNoxe2x80x9d at the step SA1, and then proceeds to step SA3. At the step SA3, the instruction issuing unit 31 issues to the memory access unit 51 load/store instructions A, B and C for the interruption level 2 buffered in the instruction buffer 21. The instruction issuing unit 31 then returns to the step SA1.
Based on this operation, the memory access unit 51 sequentially executes by pipeline processing the load/store instructions A, B and C in one clock cycle, as shown in FIG. 25C. In this case, the memory access unit 51 outputs the busy signal BUSY1 to the instruction issuing unit 31.
When the interruption level 2 has been changed to the interruption level 1 at the time t2 shown in FIG. 25B, a synchronization signal S (refer to FIG. 25C) is output. Then, the instruction issuing unit 31 makes a decision of xe2x80x9cYesxe2x80x9d at the step SA1, and then proceeds to step SA2. At the step SA2, the instruction issuing unit 31 makes a decision as to whether there has been input the busy signal BUSY1 or not.
In this case, the pipeline processing relating to the load/store instructions A, B and C is being executed, and the busy signal BUSY1 is being input, as shown in FIG. 25C. Therefore, the instruction issuing unit 31 makes a decision of xe2x80x9cNoxe2x80x9d at the step SA2, and repeats a similar process of making a decision. In other words, during the period while the synchronization signal S is being issued and the busy signal BUSY1 is being input, there arises a space in the pipe (refer to a meshed portion), as shown in FIG. 25C. This generates a loss.
When the pipeline processing relating to the load/store instructions A, B and C shown in FIG. 25C has been finished, the input of the busy signal BUSY1 is stopped. Therefore, the instruction issuing unit 31 makes a decision of xe2x80x9cNoxe2x80x9d at the step SA2, and proceeds to step SA3.
At the step SA3, the instruction issuing unit 31 issues to the memory access unit 51 load/store instructions D, E and F for the interruption level 1 buffered in the instruction buffer 21, and then returns to the step SA1. Based on this operation, the memory access unit 51 sequentially executes by pipeline processing the load/store instructions D, E and F in one clock cycle, as shown in FIG. 25C.
As explained above, according to the conventional processing unit, when the interruption level has been changed, a synchronization control is carried out regardless of the presence or absence of a change in the memory model. FIG. 29 is a diagram that shows a conventional relationship between the shift of a memory model and the presence or absence of a synchronization control. As can be understood from this drawing, according to the conventional processing unit, a synchronization control is always carried out regardless of the shift (0xe2x86x920, 0xe2x86x921, 1xe2x86x920, and 1xe2x86x921) of the memory model following the change in the interruption level.
It has been explained in the above that, according to the conventional processing unit, when the interruption level has been changed, a synchronization control is carried out without an exception, as shown in FIG. 25B and FIG. 25C. This synchronization control is effective from the viewpoint of preventing an erroneous operation due to an erroneous replacement of the sequence of executing instructions when a memory model has also been changed along with a change in the interruption level. When there has been no change in the memory model from before a change in the interruption level to after the change in the interruption level, the processing unit operates normally without carrying out the synchronization control.
However, according to the conventional processing unit, when the interruption level has been changed, the processing unit carries out the synchronization control indiscriminately without taking the memory model into consideration. Accordingly, the synchronization control is carried out unconditionally even if it is not necessary to carry out the synchronization control (that is, when there has been no change in the memory model). In this case, there arises a space in the pipe by the synchronization control, as shown in FIG. 25C, and this generates an unnecessary waiting for the execution of the instructions. Therefore, the conventional processing unit has had a problem that its processing capacity is lowered unnecessarily.
It is an object of this invention to provide a processing unit which can improve its processing capacity.
In order to achieve the above object, according to a first aspect of the present invention, there is provided a processing unit that can execute memory access instructions at a plurality of stages of interruption levels and that carries out a memory access according to a memory access sequencing model that prescribes a limit to the sequence of issuing the memory access instructions and the sequence of executing the memory access instructions, the processing unit comprising: an interruption level monitoring unit (corresponding to a synchronization instruction signal generator circuit 30 in a first embodiment to be described later) that monitors a change in the interruption levels; a memory access sequencing model monitoring unit (corresponding to the synchronization instruction signal generator circuit 30 in the first embodiment to be described later) that monitors a change in the memory access sequencing model; and a control unit (corresponding to an instruction issuing unit 121 in the first embodiment to be described later) that restricts the issuing of memory access instructions corresponding to a interruption level after a change until when the execution of memory access instructions issued before the change in the interruption level has been finished, when there has been a change in the memory access sequencing model following the change in the interruption level, based on a result of monitoring by the interruption level monitoring unit and a result of monitoring by the memory access sequencing model monitoring unit.
According to the first aspect, when the memory access sequencing model has been changed following a change in the interruption level, the control unit executes a synchronization control that restricts the issuing of memory access instructions corresponding to the interruption level after the change until when the execution of the memory access instructions issued before the change in the interruption level has been finished. Therefore, even if the interruption level has been changed, the synchronization control is not executed when the memory access sequencing model has not been changed.
As explained above, according to the first aspect, it is monitored whether there has been a change in the memory access sequencing model from before a change in the interruption level to after the change in the interruption level. The synchronization control is carried out only when the memory access sequencing model has been changed. On the other hand, when the memory access sequencing model has not been changed, the synchronization control is not carried out. Therefore, as compared with the conventional processing unit which unconditionally carries out the synchronization control when the interruption level has been changed, the processing unit of the first aspect of the invention can reduce the number of executing the synchronization control. Therefore, it is possible to improve the processing capacity.
According to a second aspect of the invention, there is provided a processing unit of the first aspect, wherein the memory access sequencing model monitoring unit compares the memory access sequencing model before a change in the interruption level with the memory access sequencing model after the change in the interruption level, and when the two memory access sequencing models do not coincide with each other, the memory access sequencing model monitoring unit changes the result of monitoring.
According to the second aspect, when a result of the comparison between the memory access sequencing model before a change in the interruption level and the memory access sequencing model after the change in the interruption level shows that the two memory access sequencing models do not coincide with each other, the memory access sequencing model monitoring unit changes the monitoring result. Accordingly, in this case, the control unit executes the synchronization control to restrict the issuing of memory access instructions corresponding to a interruption level after the change until when the execution of memory access instructions issued before the change in the interruption level has been finished.
As explained above, according to the second aspect, a decision is made as to whether or not there has been a change in the memory model from before a change in the interruption level to after the change in the interruption level. The synchronization control is carried out only when the memory model has been changed. On the other hand, when the memory model has not been changed, the synchronization control is not carried out. Therefore, as compared with the conventional processing unit which unconditionally carries out the synchronization control when the interruption level has been changed, the processing unit of the second aspect of the invention can reduce the number of executing the synchronization control. Therefore, it is possible to improve the processing capacity.
According to a third aspect of the invention, there is provided a processing unit of the first aspect, wherein the control unit (corresponding to an instruction issuing unit 121 in a second embodiment to be described later) restricts the issuing of memory access instructions corresponding to the interruption level after the change until when the execution of the memory access instructions issued before the change in the interruption level has been finished, only when the memory access sequencing model has been changed so that the limit prescribed by the memory access sequencing model is mitigated along with the change in the interruption level, based on a result of monitoring by the interruption level monitoring unit and a result of monitoring by the memory access sequencing model monitoring unit.
According to the third aspect, when the memory access sequencing model has been changed so that the limit prescribed by the memory access sequencing model is mitigated along with the change in the interruption level, the control unit executes the synchronization control to restrict the issuing of memory access instructions corresponding to the interruption level after the change until when the execution of the memory access instructions issued before the change in the interruption level has been finished. Accordingly, the synchronization control is not carried out when the memory access sequencing model has not been changed, or when the limit prescribed by the memory access sequencing model becomes severer even if the memory access sequencing model has been changed.
As explained above, according to the third aspect, it is monitored whether there has been a change in the memory access sequencing model from before a change in the interruption level to after the change in the interruption level. The synchronization control is carried out only when the memory access sequencing model has been changed so that the limit prescribed by the memory access sequencing model is mitigated. Therefore, as compared with the conventional processing unit which unconditionally carries out the synchronization control when the interruption level has been changed, the processing unit of the third aspect of the invention can reduce the number of executing the synchronization control. Therefore, it is possible to substantially improve the processing capacity.
According to a fourth aspect of the invention, there is provided a processing unit of the third aspect, wherein the memory access sequencing model monitoring unit (corresponding to the synchronization instruction signal generator circuit 2011 in the second embodiment to be described later) obtains a monitoring result based on a result of a comparison between a limit in the memory access sequencing model before a change in the interruption level and a limit in the memory access sequencing model after the change in the interruption level.
According to the fourth aspect of the invention, the memory access sequencing model monitoring unit obtains a monitoring result based on a result of a comparison between a limit in the memory access sequencing model before a change in the interruption level and a limit in the memory access sequencing model after the change in the interruption level. The control unit executes the synchronization control to restrict the issuing of memory access instructions corresponding to the interruption level after the change until when the execution of memory access instructions issued before the change in the interruption level has been finished, based on this monitoring result. Accordingly, the synchronization control is not carried out when the memory access sequencing model has not been changed, or when the limit prescribed by the memory access sequencing model becomes severer even if the memory access sequencing model has been changed.
As explained above, according to the fourth aspect, it is monitored whether there has been a change in the memory access sequencing model from before a change in the interruption level to after the change in the interruption level. The synchronization control is carried out only when the memory access sequencing model has been changed so that the limit prescribed by the memory access sequencing model is mitigated. Therefore, as compared with the conventional processing unit which unconditionally carries out the synchronization control when the interruption level has been changed, the processing unit of the third aspect of the invention can reduce the number of executing the synchronization control. Therefore, it is possible to substantially improve the processing capacity.
According to a fifth aspect of the invention, there is provided a processing unit comprising: a plurality of interruption level memory units (corresponding to a memory model setting register 3122 for the interruption level 2 to a memory model setting register 3124 for the interruption level 4 in a third embodiment to be described later) that are provided corresponding to a plurality of stages of interruption levels respectively and that store data of memory access sequencing models at the interruption levels; a common memory unit (corresponding to a common memory model setting register 313 in the third embodiment to be described later) that stores data of the memory access sequencing models; a control unit that, following a change in a interruption level, writes data of the memory access sequencing models stored in the common memory unit into the interruption level memory units corresponding to a interruption level after a change, and writes back into the common memory unit the data of the memory access sequencing models written in the interruption level memory units, when the interruption level returns to the original interruption level; an overwrite monitoring unit (corresponding to a synchronization instruction signal generator 350 in the third embodiment to be described later) that monitors an overwriting of data of the memory access sequencing models into the interruption level memory units and the common memory unit; and a control unit (corresponding to the synchronization instruction signal generator 350 in the third embodiment to be described later) that restricts the issuing of memory access instructions corresponding to a interruption level after a change until when the execution of memory access instructions issued before the change in the interruption level has been finished, when there has been an overwriting of the data of the memory access sequencing models, based on a result of monitoring by the overwrite monitoring unit.
According to the fifth aspect of the invention, when an interruption level has been changed, the data of a memory access sequencing model stored in the common memory unit is written into the interruption level memory unit corresponding to the interruption level after the change in the interruption level. When the interruption level has recovered to the original interruption level, the data of the memory access sequencing model written in the interruption level memory unit is written back, to the common memory unit. Further, during the period from the writing to the writing back, the overwrite monitoring unit monitors the overwriting of the data of the memory access sequencing model into the interruption level memory unit and the common memory unit.
Further, when the data of the memory access sequencing model has been overwritten, the control unit restricts the issuing of memory access instructions corresponding to a interruption level after a change until when the execution of memory access instructions issued before the change in the interruption level has been finished. Accordingly, the synchronization control is not executed when the data has not been overwritten into the interruption level memory unit and the common memory unit even if the interruption level has been changed. In other words, when the memory access sequencing model has not been changed, the synchronization control is not executed.
As explained above, according to the fifth aspect of the invention, the synchronization control is carried out only when the data of the memory access sequencing model has been overwritten into the interruption level memory unit and the common memory unit. Therefore, as compared with the conventional processing unit which unconditionally carries out the synchronization control when the interruption level has been changed, the processing unit of the fifth aspect of the invention can reduce the number of executing the synchronization control. Therefore, it is possible to improve the processing capacity.
According to a sixth aspect of the invention, there is provided a processing unit of the fifth aspect, wherein the control unit (corresponding to a synchronization instruction signal generator 350 in a fourth embodiment to be described later) restricts the issuing of memory access instructions corresponding to a interruption level after a change until when the execution of memory access instructions issued before the change in the interruption level has been finished, by making a decision that there has been an updating of data when the data before the overwriting does not coincide with the data after the overwriting, based on a result of monitoring by the overwrite monitoring unit.
According to the sixth aspect of the invention, when an interruption level has been changed, the data of a memory access sequencing model stored in the common memory unit is written into the interruption level memory unit corresponding to the interruption level after the change in the interruption level. When the interruption level has recovered to the original interruption level, the data of the memory access sequencing model written in the interruption level memory unit is written back to the common memory unit. Further, during the period from the writing to the writing back, the overwrite monitoring unit monitors the overwriting of the data of the memory access sequencing model into the interruption level memory unit and the common memory unit.
Further, when the data of the memory access sequencing model has been overwritten and also when the data has been updated, the control unit restricts the issuing of memory access instructions corresponding to a interruption level after a change until when the execution of memory access instructions issued before the change in the interruption level has been finished. Accordingly, the synchronization control is not executed when the data has not been updated even if the data has been overwritten into the interruption level memory unit and the common memory unit. In other words, when the memory access sequencing model has not been changed, the synchronization control is not executed.
As explained above, according to the sixth aspect of the invention, the synchronization control is carried out only when the data of the memory access sequencing model has been overwritten into the interruption level memory unit and the common memory unit and also when the data has been updated. Therefore, as compared with the conventional processing unit which unconditionally carries out the synchronization control when the interruption level has been changed, the processing unit of the sixth aspect of the invention can reduce the number of executing the synchronization control. Therefore, it is possible to substantially improve the processing capacity.
According to a seventh aspect of the invention, there is provided a processing unit that can at least execute memory access instructions at a plurality of stages of interruption levels and that carries out a memory access according to a memory access sequencing model that prescribes a limit to the sequence of issuing the memory access instructions and the sequence of executing the memory access instructions, the processing unit comprising: an interruption level monitoring unit that monitors a change in the interruption levels; a memory access sequencing model monitoring unit that monitors a change in the memory access sequencing model; and a control unit that executes instructions other than memory access instructions issued after a change in a memory access sequencing model prior to the execution of the memory access instructions, and that restricts the issuing of memory access instructions corresponding to a interruption level after a change until when the execution of memory access instructions issued before the change in the interruption level has been finished, when there has been a change in the memory access sequencing model following the change in the interruption level, based on a result of monitoring by the interruption level monitoring unit and a result of monitoring by the memory access sequencing model monitoring unit.
According to the seventh aspect, when the memory access sequencing model has been changed following a change in the interruption level, the control unit executes instructions other than memory access instructions issued after a change in the memory access sequencing model prior to the execution of the memory access instructions, and restricts the issuing of memory access instructions corresponding to the interruption level after the change until when the execution of memory access instructions issued before the change in the interruption level has been finished. Therefore, even if the interruption level has been changed, the synchronization control is not executed when the memory access sequencing model has not been changed.
As explained above, according to the seventh aspect of the invention, the synchronization control is carried out only when the interruption level has been changed and also when the memory access instructions have been issued. Therefore, when instructions other than memory access instructions (for example, processing instructions) have been issued, these instructions are executed prior to the synchronization control. As a result, it is possible to improve the processing capacity.